The CMOS structure is analyzed and the PNP and NPN latching transistors are identified. The CMOS latch schematic is drawn and the triggering methods are discussed. Some ways to reduce latch up are presented.
Home Page
The CMOS structure is analyzed and the PNP and NPN latching transistors are identified. The CMOS latch schematic is drawn and the triggering methods are discussed. Some ways to reduce latch up are presented.
Home Page